High gain two-stage amplifier with positive capacitive feedback compensation

TL;DR

This paper introduces a high gain two-stage amplifier with positive capacitive feedback that improves stability, bandwidth, and slew rate, suitable for low-power CMOS applications.

Contribution

A novel amplifier topology with PCF compensation that cancels phase shift and enhances slew rate, demonstrating high gain and stability in 0.18um CMOS process.

Findings

DC gain of 82.7dB achieved

Gain bandwidth of 88.9 MHz with 5pF load

Slew rate improved by a factor of 2.44

Abstract

A novel topology for a high gain two-stage amplifier is proposed. The proposed circuit is designed in a way that the non-dominant pole is at output of the first stage. A positive capacitive feedback (PCF) around the second stage introduces a left half plane (LHP) zero which cancels the phase shift introduced by the non-dominant pole, considerably. The dominant pole is at the output node which means that increasing the load capacitance has minimal effect on stability. Moreover, a simple and effective method is proposed to enhance slew rate. Simulation shows that slew rate is improved by a factor of 2.44 using the proposed method. The proposed amplifier is designed in a 0.18um CMOS process. It consumes 0.86mW power from a 1.8V power supply and occupies 3038.5um2 of chip area. The DC gain is 82.7dB and gain bandwidth (GBW) is 88.9 MHz when driving a 5pF capacitive load. Also low frequency CMRR and PSRR+ are 127dB and 83.2dB, respectively. They are 24.8dB and 24.2dB at GBW frequency, which are relatively high and are other important properties of the proposed amplifier. Moreover, Simulations show convenient performance of the circuit in process corners and also presence of mismatch.