Designing high-speed, low-power full adder cells based on carbon nanotube technology

TL;DR

This paper introduces four novel high-speed, low-power full adder designs based on carbon nanotube FET technology, optimized for performance by adjusting CNFET diameters, and compares their efficiency to existing designs.

Contribution

It proposes four new CNFET-based full adder architectures with optimized threshold control, demonstrating improved speed and power efficiency over traditional CMOS and CNFET designs.

Findings

CN10PFS design achieves full swing operation with only 10 transistors.

All proposed designs show reduced delay and power consumption compared to classical counterparts.

Parallel signal generation in CN8P10G enhances performance and efficiency.

Abstract

This article presents novel high speed and low power full adder cells based on carbon nanotube field effect transistor (CNFET). Four full adder cells are proposed in this article. First one (named CN9P4G) and second one (CN9P8GBUFF) utilizes 13 and 17 CNFETs respectively. Third design that we named CN10PFS uses only 10 transistors and is full swing. Finally, CN8P10G uses 18 transistors and divided into two modules, causing Sum and Cout signals are produced in a parallel manner. All inputs have been used straight, without inverting. These designs also used the special feature of CNFET that is controlling the threshold voltage by adjusting the diameters of CNFETs to achieve the best performance and right voltage levels. All simulation performed using Synopsys HSPICE software and the proposed designs are compared to other classical and modern CMOS and CNFET-based full adder cells in terms of delay, power consumption and power delay product.