Energy Efficient Full Adder Cell Design With Using Carbon Nanotube Field Effect Transistors In 32 Nanometer Technology

TL;DR

This paper proposes a low-power full adder design using carbon nanotube field effect transistors (CNTFETs) in 32nm technology, aiming to reduce power consumption and chip area in digital circuits.

Contribution

It introduces a novel full adder cell utilizing CNTFETs and evaluates its performance through simulations in various conditions.

Findings

Significant power reduction compared to traditional designs

Effective operation across different temperatures and voltages

Potential for energy-efficient nano-scale circuit applications

Abstract

Full Adder is one of the critical parts of logical and arithmetic units. So, presenting a low power full adder cell reduces the power consumption of the entire circuit. Also, using Nano-scale transistors, because of their unique characteristics will save energy consumption and decrease the chip area. In this paper we presented a low power full adder cell by using carbon nanotube field effect transistors (CNTFETs). Simulation results were carried out using HSPICE based on the CNTFET model in 32 nanometer technology in Different values of temperature and VDD.