Programming the Adapteva Epiphany 64-core Network-on-chip Coprocessor

TL;DR

This paper evaluates the Epiphany 64-core network-on-chip coprocessor's performance and explores programming strategies for its low-power, memory-constrained architecture, assessing its potential for exascale computing.

Contribution

It provides an empirical performance analysis and explores programming approaches for the Epiphany architecture, highlighting its suitability for energy-efficient high-performance computing.

Findings

Epiphany achieves high GFLOPS/Watt efficiency.

Memory constraints significantly impact programming strategies.

Potential for exascale systems with thousands of cores.

Abstract

In the construction of exascale computing systems energy efficiency and power consumption are two of the major challenges. Low-power high performance embedded systems are of increasing interest as building blocks for large scale high- performance systems. However, extracting maximum performance out of such systems presents many challenges. Various aspects from the hardware architecture to the programming models used need to be explored. The Epiphany architecture integrates low-power RISC cores on a 2D mesh network and promises up to 70 GFLOPS/Watt of processing efficiency. However, with just 32 KB of memory per eCore for storing both data and code, and only low level inter-core communication support, programming the Epiphany system presents several challenges. In this paper we evaluate the performance of the Epiphany system for a variety of basic compute and communication operations. Guided by this data we explore strategies for implementing scientific applications on memory constrained low-powered devices such as the Epiphany. With future systems expected to house thousands of cores in a single chip, the merits of such architectures as a path to exascale is compared to other competing systems.