Analogue Sum ASIC for L1 Trigger Decision in Cherenkov Telescope Cameras

TL;DR

This paper presents an ASIC design for the Level 1 trigger system in Cherenkov Telescope Array cameras, enhancing performance, noise reduction, and power efficiency over previous discrete-component prototypes.

Contribution

The first ASIC implementation for CTA's Level 1 trigger system, adaptable to various strategies and optimized for noise, bandwidth, dynamic range, and power consumption.

Findings

ASIC meets CTA requirements for noise and bandwidth

Improves compactness and power efficiency over prototypes

Compatible with different trigger strategies

Abstract

The Cherenkov Telescope Array (CTA) project aims to build the largest ground-based gamma-ray observatory based on an array of Imaging Atmospheric Cherenkov Telescopes (IACTs). The CTA will implement a multi-level trigger system to distinguish between gamma ray-like induced showers and background images induced by night sky background (NSB) light. The trigger system is based on coincident detections among pixels (level 0 trigger), clusters of pixels (level 1) or telescopes. In this article, the first version of the application specific integrated circuit (ASIC) for Level 1 trigger system is presented, capable of working with different Level 0 strategies and different trigger region sizes. In addition, it complies with all the requirements specified by the CTA project, specially the most critical ones as regards noise, bandwidth, dynamic range and power consumption. All these features make the presented system very suitable for use in the CTA cameras and improve the features of discrete components prototypes of the L1 trigger circuit in terms of compactness, noise, performance and power consumption.