A Data Readout Approach for Physics Experiment

TL;DR

This paper presents a high-speed Ethernet-based data readout system for physics experiments, utilizing parallel transmission, FPGA reconfiguration, and embedded CPU processing to achieve up to 70 Mbps data throughput.

Contribution

It introduces a novel Ethernet-based readout architecture with FPGA and embedded CPU integration for enhanced speed and flexibility in physics experiments.

Findings

Supports up to 70 Mbps data throughput

Uses FPGA for flexible protocol handling

Employs SRAM-based interface optimization

Abstract

With the increasing physical event rate and number of electronic channels, traditional readout scheme meets the challenge of improving readout speed caused by the limited bandwidth of crate backplane. In this paper, a high-speed data readout method based on Ethernet is designed for each module to have capability of transmitting data to DAQ. Features of explicitly parallel data transmitting and distributed network architecture make the readout system has advantage of adapting varying requirements of particle physics experiments. Furthermore, to guarantee the readout performance and flexibility, a standalone embedded CPU system is utilized for network protocol stack processing. To receive customized data format and protocol from front-end electronics, a field programmable gate array (FPGA) is used for logic reconfiguration. To optimize the interface and improve the data swap speed between CPU and FPGA, a sophisticated method based on SRAM is presented in this paper. For the purpose of evaluating this high-speed readout method, a simplified readout module is designed and implemented. Test results show that this module can support up to 70Mbps data throughput from the readout module to DAQ smoothly.