Redesigning Commercial Floating-Gate Memory for Analog Computing Applications

TL;DR

This paper presents a modified commercial floating-gate memory array optimized for high-precision analog computing, achieving automatic tuning with 1% accuracy and demonstrating a linear vector-matrix multiplication prototype.

Contribution

It introduces a novel modification to commercial NOR flash memory for precise analog tuning, enabling efficient analog computing applications.

Findings

Successful automatic tuning of cells to 1% precision

Memory array size is significantly smaller than traditional analog circuits

Prototype vector-by-matrix multiplier shows highly linear transfer characteristics

Abstract

We have modified a commercial NOR flash memory array to enable high-precision tuning of individual floating-gate cells for analog computing applications. The modified array area per cell in a 180 nm process is about 1.5 um^2. While this area is approximately twice the original cell size, it is still at least an order of magnitude smaller than in the state-of-the-art analog circuit implementations. The new memory cell arrays have been successfully tested, in particular confirming that each cell may be automatically tuned, with ~1% precision, to any desired subthreshold readout current value within an almost three-orders-of-magnitude dynamic range, even using an unoptimized tuning algorithm. Preliminary results for a four-quadrant vector-by-matrix multiplier, implemented with the modified memory array gate-coupled with additional peripheral floating-gate transistors, show highly linear transfer characteristics over a broad range of input currents.