Analysis and Design of Finite Alphabet Iterative Decoders Robust to Faulty Hardware

TL;DR

This paper develops a framework for designing LDPC decoders that are resilient to transient hardware errors, analyzing their behavior and robustness through theoretical models and simulations.

Contribution

It introduces a general framework for faulty message update functions, analyzes their symmetry and error models, and proposes a method to design robust finite alphabet decoders.

Findings

Functional Density Evolution threshold has limitations with highly unreliable hardware.

Under certain noise conditions, the functional threshold predicts decoder convergence.

Robust and non-robust FAIDs exhibit distinct behaviors in simulations.

Abstract

This paper addresses the problem of designing LDPC decoders robust to transient errors introduced by a faulty hardware. We assume that the faulty hardware introduces errors during the message passing updates and we propose a general framework for the definition of the message update faulty functions. Within this framework, we define symmetry conditions for the faulty functions, and derive two simple error models used in the analysis. With this analysis, we propose a new interpretation of the functional Density Evolution threshold previously introduced, and show its limitations in case of highly unreliable hardware. However, we show that under restricted decoder noise conditions, the functional threshold can be used to predict the convergence behavior of FAIDs under faulty hardware. In particular, we reveal the existence of robust and non-robust FAIDs and propose a framework for the design of robust decoders. We finally illustrate robust and non-robust decoders behaviors of finite length codes using Monte Carlo simulations.