A Complementary Resistive Switch-based Crossbar Array Adder

TL;DR

This paper presents two novel multi-bit adder schemes using complementary resistive switches (CRSs) in ReRAM crossbar arrays, demonstrating improved efficiency over previous ReRAM-based logic approaches through SPICE simulations.

Contribution

It introduces innovative multi-bit adder schemes based on CRS technology for ReRAM arrays, enhancing logic-in-memory capabilities and efficiency.

Findings

CRS-based adders outperform previous ReRAM logic methods in step count.

Simulations confirm the feasibility of multi-bit addition with CRS devices.

Advantages include reduced device count and improved operational speed.

Abstract

Redox-based resistive switching devices (ReRAM) are an emerging class of non-volatile storage elements suited for nanoscale memory applications. In terms of logic operations, ReRAM devices were suggested to be used as programmable interconnects, large-scale look-up tables or for sequential logic operations. However, without additional selector devices these approaches are not suited for use in large scale nanocrossbar memory arrays, which is the preferred architecture for ReRAM devices due to the minimum area consumption. To overcome this issue for the sequential logic approach, we recently introduced a novel concept, which is suited for passive crossbar arrays using complementary resistive switches (CRSs). CRS cells offer two high resistive storage states, and thus, parasitic sneak currents are efficiently avoided. However, until now the CRS-based logic-in-memory approach was only shown to be able to perform basic Boolean logic operations using a single CRS cell. In this paper, we introduce two multi-bit adder schemes using the CRS-based logic-in-memory approach. We proof the concepts by means of SPICE simulations using a dynamical memristive device model of a ReRAM cell. Finally, we show the advantages of our novel adder concept in terms of step count and number of devices in comparison to a recently published adder approach, which applies the conventional ReRAM-based sequential logic concept introduced by Borghetti et al.