Analysis of boundary point (break point) in Linear Delay Model for nanoscale VLSI standard cell library characterization at PVT corners
Gaurav Kumar Agarwal

TL;DR
This paper analyzes the boundary point in a linear delay model for nanoscale VLSI standard cell characterization, providing a formula to determine it at various PVT corners to reduce LUT characterization time.
Contribution
It introduces a formula to accurately find the break point in the linear delay model across PVT corners, enhancing LUT characterization efficiency.
Findings
Derived a formula for the break point at PVT corners.
Reducing LUT simulation time by focusing on non-linear region.
Improved efficiency in delay model characterization.
Abstract
In VLSI chip design flow, Static Timing Analysis (STA) is used for fast and accurate analysis of data-path delay. This process is fast because delay is picked from Look Up Tables (LUT) rather than conventional SPICE simulations. But accuracy of this method depends upon the underlying delay model with which LUT was characterized. Non Linear Delay Model (NLDM) based LUTs are quite common in industries. These LUT requires huge amount to time during characterization because of huge number of SPICE simulations done at arbitrary points. To improve this people proposed various other delay models like alpha-power and piecewise linear delay models. Bulusu et al proposed Linear Delay Model(LDM) which reduces LUT generation time to 50 percent. LDM divides delay curve w.r.t input rise time(trin) into two different region one is linear and other is non-linear. This boundary point between linear and…
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Taxonomy
TopicsLow-power high-performance VLSI design · VLSI and Analog Circuit Testing · VLSI and FPGA Design Techniques
