An ECG-on-Chip for Wearable Cardiac Monitoring Devices

TL;DR

This paper presents a highly integrated, low-power ECG-on-chip solution designed for wearable cardiac monitoring, featuring analog front end, signal processing, and memory components in a compact CMOS design.

Contribution

The paper introduces a novel low-power, highly integrated ECG chip with on-chip signal processing and memory, optimized for wearable health monitoring devices.

Findings

Chip consumes only 9.6μW power

Operates at 256 Hz sampling frequency

Total area of 5.74 mm^2 in 0.35μm CMOS

Abstract

This paper describes a highly integrated, low power chip solution for ECG signal processing in wearable devices. The chip contains an instrumentation amplifier with programmable gain, a band-pass filter, a 12-bit SAR ADC, a novel QRS detector, 8K on-chip SRAM, and relevant control circuitry and CPU interfaces. The analog front end circuits accurately senses and digitizes the raw ECG signal, which is then filtered to extract the QRS. The sampling frequency used is 256 Hz. ECG samples are buffered locally on an asynchronous FIFO and is read out using a faster clock, as and when it is required by the host CPU via an SPI interface. The chip was designed and implemented in 0.35um standard CMOS process. The analog core operates at 1V while the digital circuits and SRAM operate at 3.3V. The chip total core area is 5.74 mm^2 and consumes 9.6uW. Small size and low power consumption make this design suitable for usage in wearable heart monitoring devices.