An Efficient Topology-Based Algorithm for Transient Analysis of Power Grid

TL;DR

This paper introduces a topology-based algorithm for transient analysis of power grids in integrated circuits, significantly improving efficiency by leveraging nodal analysis and proven convergence.

Contribution

It presents a novel topology-based method for power grid transient analysis that reduces computational cost and is mathematically validated for convergence.

Findings

Reduces analysis time compared to traditional methods

Proven convergence of the proposed algorithm

Applicable to large-scale power grid verification

Abstract

In the design flow of integrated circuits, chip-level verification is an important step that sanity checks the performance is as expected. Power grid verification is one of the most expensive and time-consuming steps of chip-level verification, due to its extremely large size. Efficient power grid analysis technology is highly demanded as it saves computing resources and enables faster iteration. In this paper, a topology-base power grid transient analysis algorithm is proposed. Nodal analysis is adopted to analyze the topology which is mathematically equivalent to iteratively solving a positive semi-definite linear equation. The convergence of the method is proved.