Stochastic Testing Method for Transistor-Level Uncertainty Quantification Based on Generalized Polynomial Chaos
Zheng Zhang, Tarek A. El-Moselhy, Ibrahim (Abe) M. Elfadel, Luca, Daniel

TL;DR
This paper introduces an efficient stochastic testing method based on generalized polynomial chaos for transistor-level uncertainty quantification, reducing computational effort compared to traditional Monte Carlo and other spectral methods.
Contribution
The paper develops an intrusive stochastic testing method that accelerates nonlinear circuit uncertainty analysis by decoupling equations and reducing sample requirements.
Findings
ST method is more efficient than SG and SC methods.
ST allows flexible time step control in time-domain simulations.
Simulation results demonstrate effectiveness on digital, analog, and RF circuits.
Abstract
Uncertainties have become a major concern in integrated circuit design. In order to avoid the huge number of repeated simulations in conventional Monte Carlo flows, this paper presents an intrusive spectral simulator for statistical circuit analysis. Our simulator employs the recently developed generalized polynomial chaos expansion to perform uncertainty quantification of nonlinear transistor circuits with both Gaussian and non-Gaussian random parameters. We modify the nonintrusive stochastic collocation (SC) method and develop an intrusive variant called stochastic testing (ST) method to accelerate the numerical simulation. Compared with the stochastic Galerkin (SG) method, the resulting coupled deterministic equations from our proposed ST method can be solved in a decoupled manner at each time point. At the same time, ST uses fewer samples and allows more flexible time step size…
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