The artificial retina processor for track reconstruction at the LHC crossing rate

TL;DR

This paper introduces a specialized FPGA-based processor capable of real-time, high-precision reconstruction of charged-particle tracks at the LHC's 40 MHz crossing rate, enabling immediate analysis of collision events.

Contribution

It presents a novel, highly parallel pattern-recognition algorithm inspired by biological vision, with an efficient hardware implementation for real-time LHC data processing.

Findings

First demonstration of offline-quality track reconstruction at 40 MHz

Successful hardware implementation in high-speed FPGA devices

Achieves precise, real-time processing suitable for LHC event rates

Abstract

We present results of an R&D study for a specialized processor capable of precisely reconstructing, in pixel detectors, hundreds of charged-particle tracks from high-energy collisions at 40 MHz rate. We apply a highly parallel pattern-recognition algorithm, inspired by studies of the processing of visual images by the brain as it happens in nature, and describe in detail an efficient hardware implementation in high-speed, high-bandwidth FPGA devices. This is the first detailed demonstration of reconstruction of offline-quality tracks at 40 MHz and makes the device suitable for processing Large Hadron Collider events at the full crossing frequency.