Massive MIMO with Non-Ideal Arbitrary Arrays: Hardware Scaling Laws and Circuit-Aware Design

TL;DR

This paper investigates how massive MIMO systems can be designed cost-effectively by allowing hardware imperfections to scale with the array size, deriving laws that enable low-power, low-cost hardware while maintaining high user rates.

Contribution

It provides a rigorous analysis of hardware imperfections in massive MIMO, deriving scaling laws that link array size, hardware quality, and power consumption, with circuit-aware design insights.

Findings

Hardware imperfections can increase with the square root of the number of antennas while maintaining performance.

Derived closed-form user rate expressions for systems with hardware impairments.

Showed that circuit power consumption can be scaled down by careful system design.

Abstract

Massive multiple-input multiple-output (MIMO) systems are cellular networks where the base stations (BSs) are equipped with unconventionally many antennas, deployed on co-located or distributed arrays. Huge spatial degrees-of-freedom are achieved by coherent processing over these massive arrays, which provide strong signal gains, resilience to imperfect channel knowledge, and low interference. This comes at the price of more infrastructure; the hardware cost and circuit power consumption scale linearly/affinely with the number of BS antennas $N$. Hence, the key to cost-efficient deployment of large arrays is low-cost antenna branches with low circuit power, in contrast to today's conventional expensive and power-hungry BS antenna branches. Such low-cost transceivers are prone to hardware imperfections, but it has been conjectured that the huge degrees-of-freedom would bring robustness to such imperfections. We prove this claim for a generalized uplink system with multiplicative phase-drifts, additive distortion noise, and noise amplification. Specifically, we derive closed-form expressions for the user rates and a scaling law that shows how fast the hardware imperfections can increase with $N$ while maintaining high rates. The connection between this scaling law and the power consumption of different transceiver circuits is rigorously exemplified. This reveals that one can make the circuit power increase as $\sqrt{N}$, instead of linearly, by careful circuit-aware system design.