Extrinsic and Intrinsic Charge Trapping at the Graphene/Ferroelectric Interface

TL;DR

This study investigates charge trapping mechanisms at the graphene/ferroelectric interface, demonstrating how intrinsic and extrinsic traps influence hysteresis behavior and how careful processing can control these effects.

Contribution

It provides new insights into charge trapping at the graphene/ferroelectric interface and shows how tuning the ferroelectric transition temperature minimizes adsorbates, enabling better control of hysteresis.

Findings

Minimized adsorbates at the interface through transition temperature tuning.

Intrinsic charge traps from surface defects affect hysteresis.

Careful sample processing enables systematic study of charge trapping.

Abstract

The interface between graphene and the ferroelectric superlattice $\mathrm{PbTiO_3/SrTiO_3}$ (PTO/STO) is studied. Tuning the transition temperature through the PTO/STO volume fraction minimizes the adsorbates at the graphene-ferroelectric interface, allowing robust ferroelectric hysteresis to be demonstrated. Intrinsic charge traps from the ferroelectric surface defects can adversely affect the graphene channel hysteresis, and can be controlled by careful sample processing, enabling systematic study of the charge trapping mechanism.