Fabrication Process and Properties of Fully-Planarized Deep-Submicron Nb/Al-AlOx/Nb Josephson Junctions for VLSI Circuits
Sergey K. Tolpygo, Vladimir Bolkhovsky, Terence J. Weir, Leonard M., Johnson, Mark A. Gouker, and William D. Oliver

TL;DR
This paper presents a new fabrication process for ultra-small Nb/Al-AlOx/Nb Josephson junctions on 200-mm wafers, achieving high uniformity and reproducibility, suitable for high-density superconducting circuits with advanced lithography techniques.
Contribution
Developed a fully-planarized fabrication process for sub-200 nm Josephson junctions compatible with CMOS foundry tools, enabling high-density superconductor integrated circuits.
Findings
Achieved 0.8% to 3% spread in critical current for 1500 nm to 500 nm JJs.
Demonstrated reproducibility and uniformity across 200-mm wafers.
Discussed prospects for circuit densities exceeding 10^6 JJs/cm².
Abstract
A fabrication process for Nb/Al-AlOx/Nb Josephson junctions (JJs) with sizes down to 200 nm has been developed on a 200-mm-wafer tool set typical for CMOS foundry. This process is the core of several nodes of a roadmap for fully-planarized fabrication processes for superconductor integrated circuits with 4, 8, and 10 niobium layers developed at MIT Lincoln Laboratory. The process utilizes 248 nm photolithography, anodization, high-density plasma etching, and chemical mechanical polishing (CMP) for planarization of SiO interlayer dielectric. JJ electric properties and statistics such as on-chip and wafer spreads of critical current, , normal-state conductance, , and run-to-run reproducibility have been measured on 200-mm wafers over a broad range of JJ diameters from 200 nm to 1500 nm and critical current densities, , from 10 kA/ to 50 kA/ where the JJs…
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