Device Perspective for Black Phosphorus Field-Effect Transistors: Contact Resistance, Ambipolar and Scaling

TL;DR

This paper investigates ultra-thin black phosphorus FETs, focusing on contact resistance, Schottky barriers, and ambipolar behavior, revealing how contact metals influence device performance and potential for CMOS applications.

Contribution

It introduces a scheme to analyze contact resistance in BP FETs, highlighting the impact of contact metals on Schottky barriers and ambipolar conduction, advancing understanding of BP device physics.

Findings

Contact resistance varies with contact metal due to Schottky barrier differences.

BP transistors exhibit ambipolar behavior with tunable n- and p-type conduction.

Scaling behavior shows contact resistance dependence on channel length.

Abstract

Although monolayer black phosphorus (BP) or phosphorene has been successfully exfoliated and its optical properties have been explored, most of electrical performance of the devices is demonstrated on few-layer phosphorene and ultra-thin BP films. In this paper, we study the channel length scaling of ultra-thin BP field-effect transistors (FETs), and discuss a scheme for using various contact metals to change transistor characteristics. Through studying transistor behaviors with various channel lengths, the contact resistance can be extracted from the transfer length method (TLM). With different contact metals, we find out that the metal/BP interface has different Schottky barrier heights, leading to a significant difference in contact resistance, which is quite different from previous studies of transition metal dichalcogenides (TMDs) such as MoS2 where Fermi-level is strongly pinned near conduction band edge at metal/MoS2 interface. The nature of BP transistors are Schottky barrier FETs, where the on and off states are controlled by tuning the Schottky barriers at the two contacts. We also observe the ambipolar characteristics of BP transistors with enhanced n-type drain current and demonstrate that the p-type carriers can be easily shifted to n-type or vice versus by controlling the gate bias and drain bias, showing the potential to realize BP CMOS logic circuits.