SAT-Based Methods for Circuit Synthesis

TL;DR

This paper explores SAT- and QBF-based techniques for circuit synthesis from strategies, demonstrating improved performance and circuit size over BDDs through optimized implementations and experimental validation.

Contribution

It introduces novel SAT- and QBF-based methods for circuit synthesis, including optimizations and implementations that outperform traditional BDD approaches.

Findings

Outperforms BDDs in execution time

Produces smaller circuits

Effective for safety specifications

Abstract

Reactive synthesis supports designers by automatically constructing correct hardware from declarative specifications. Synthesis algorithms usually compute a strategy, and then construct a circuit that implements it. In this work, we study SAT- and QBF-based methods for the second step, i.e., computing circuits from strategies. This includes methods based on QBF-certification, interpolation, and computational learning. We present optimizations, efficient implementations, and experimental results for synthesis from safety specifications, where we outperform BDDs both regarding execution time and circuit size. This is an extended version of [2], with an additional appendix.