Gating of high-mobility InAs metamorphic heterostructures

TL;DR

This paper explores gating in high-mobility InAs heterostructures, introduces a technique to estimate surface charge, and demonstrates that using InAlAs barriers reduces parallel conduction, enabling better device control.

Contribution

It presents a new method to estimate surface charge density and shows that InAlAs barriers significantly reduce parallel conduction in InAs heterostructures.

Findings

Parallel conduction can be estimated via cool-down with gate bias.

InAlAs barriers drastically reduce parallel conduction.

Full depletion with non-hysteretic gating is achievable using InAlAs.

Abstract

We investigate the performance of gate-defined devices fabricated on high mobility InAs metamorphic heterostructures. We find that heterostructures capped with In$_{0.75}$Ga$_{0.25}$As often show signs of parallel conduction due to proximity of their surface Fermi level to the conduction band minimum. Here, we introduce a technique that can be used to estimate the density of this surface charge that involves cool-downs from room temperature under gate bias. We have been able to remove the parallel conduction under high positive bias, but achieving full depletion has proven difficult. We find that by using In$_{0.75}$Al$_{0.25}$As as the barrier without an In$_{0.75}$Ga$_{0.25}$As capping, a drastic reduction in parallel conduction can be achieved. Our studies show that this does not change the transport properties of the quantum well significantly. We achieved full depletion in InAlAs capped heterostructures with non-hysteretic gating response suitable for fabrication of gate-defined mesoscopic devices.