Early Development of UVM based Verification Environment of Image Signal Processing Designs using TLM Reference Model of RTL

TL;DR

This paper proposes a novel approach for early development of reusable UVM-based verification environments for image signal processing designs, utilizing TLM reference models to accelerate verification and improve coverage.

Contribution

It introduces a multi-language verification flow that enables early creation of verification components and test vectors before RTL availability, enhancing reusability and verification efficiency.

Findings

Early verification environment development accelerates project timelines.

Reusable verification components improve coverage and reduce effort.

The approach is extendable to non-image signal processing designs.

Abstract

With semiconductor industry trend of smaller the better, from an idea to a final product, more innovation on product portfolio and yet remaining competitive and profitable are few criteria which are culminating into pressure and need for more and more innovation for CAD flow, process management and project execution cycle. Project schedules are very tight and to achieve first silicon success is key for projects. This necessitates quicker verification with better coverage matrix. Quicker Verification requires early development of the verification environment with wider test vectors without waiting for RTL to be available. In this paper, we are presenting a novel approach of early development of reusable multi-language verification flow, by addressing four major activities of verification like Early creation of Executable Specification, Early creation of Verification Environment, Early development of test vectors and Better and increased Re-use of blocks. Although this paper focuses on early development of UVM based Verification Environment of Image Signal Processing designs using TLM Reference Model of RTL, same concept can be extended for non-image signal processing designs. Main Keywords are SystemVerilog, SystemC, Transaction Level Modeling, Universal Verification Methodology (UVM), Processor model, Universal Verification Component (UVC), Reference Model.