Probing limits of STM field emission patterned Si:P $\delta$-doped devices

TL;DR

This paper investigates the use of high voltage field emission mode in STM for rapid patterning of Si:P delta-doped devices, demonstrating that increased speed does not compromise device functionality at larger scales and enhances nanoscale device definition.

Contribution

It introduces a high voltage field emission mode for STM patterning, significantly increasing patterning speed while maintaining device quality at micron and nanometer scales.

Findings

High voltage mode increases patterning speed by over 100 times.

Large features remain functional despite rapid patterning.

Nanoscale features achieve 10 nm precision despite 40 nm spot size.

Abstract

Recently, a single atom transistor was deterministically fabricated using phosphorus in Si by H-desorption lithography with a scanning tunneling microscope (STM). This milestone in precision, achieved by operating the STM in the conventional tunneling mode, typically utilizes very slow ($\sim\!10^2~\mathrm{nm^2/s}$) patterning speeds. By contrast, using the STM in a high voltage ($>10~\mathrm{V}$) field emission mode, patterning speeds can be increased by orders of magnitude to $\gtrsim\!10^4~\mathrm{nm^2/s}$. We show that the rapid patterning negligibly affects the functionality of relatively large micron-sized features, which act as contacting pads on these devices. For nanoscale structures, we show that the resulting transport is consistent with the donor incorporation chemistry enhancing the device definition to a scale of $10~\mathrm{nm}$ even though the pattering spot size is $40~\mathrm{nm}$.