Parallelism-Aware Memory Interference Delay Analysis for COTS Multicore Systems

TL;DR

This paper presents a new analysis method for accurately estimating worst-case memory interference delays in COTS multicore systems, considering parallel requests, LLC, and DRAM controller behaviors.

Contribution

It introduces a novel model and analysis that provide safer upper bounds for memory interference delay in modern COTS multicore platforms.

Findings

More accurate worst-case delay estimation

Safer upper bounds compared to previous analysis

Validated on real multicore hardware with benchmarks

Abstract

In modern Commercial Off-The-Shelf (COTS) multicore systems, each core can generate many parallel memory requests at a time. The processing of these parallel requests in the DRAM controller greatly affects the memory interference delay experienced by running tasks on the platform. In this paper, we model a modern COTS multicore system which has a nonblocking last-level cache (LLC) and a DRAM controller that prioritizes reads over writes. To minimize interference, we focus on LLC and DRAM bank partitioned systems. Based on the model, we propose an analysis that computes a safe upper bound for the worst-case memory interference delay. We validated our analysis on a real COTS multicore platform with a set of carefully designed synthetic benchmarks as well as SPEC2006 benchmarks. Evaluation results show that our analysis is more accurately capture the worst-case memory interference delay and provides safer upper bounds compared to a recently proposed analysis which significantly under-estimate the delay.