Efficient Design of Reversible Sequential Circuit

TL;DR

This paper introduces two new reversible logic gates and uses them to design more efficient reversible latches and flip-flops, improving on existing designs in gate count, garbage outputs, and delay.

Contribution

The paper proposes two novel reversible logic gates and new design techniques for sequential memory elements, enhancing efficiency over prior methods.

Findings

Reduced gate count in designs

Fewer garbage outputs

Lower delay in reversible flip-flops

Abstract

Reversible logic has come to the forefront of theoretical and applied research today. Although many researchers are investigating techniques to synthesize reversible combinational logic, there is little work in the area of sequential reversible logic. Latches and flip-flops are the most significant memory elements for the forthcoming sequential memory elements. In this paper, we proposed two new reversible logic gates MG-1 and MG-2. We then proposed new design techniques for latches and flip-flops with the help of the new proposed gates. The proposed designs are better than the existing ones in terms of number of gates, garbage outputs and delay.