FPGA Based Efficient Multiplier for Image Processing Applications Using Recursive Error Free Mitchell Log Multiplier and KOM Architecture

TL;DR

This paper introduces an FPGA-based recursive error-free Mitchell Log multiplier integrated with KOM architecture, significantly enhancing speed and accuracy for image processing tasks like noise reduction in fingerprint images.

Contribution

It presents a novel FPGA implementation of an error-free Mitchell Log multiplier combined with KOM architecture for high-speed, accurate image processing applications.

Findings

Reduced error rate compared to existing multipliers

Improved speed and area efficiency on FPGA

Enhanced PSNR in fingerprint image filtering

Abstract

The Digital Image processing applications like medical imaging, satellite imaging, Biometric trait images etc., rely on multipliers to improve the quality of image. However, existing multiplication techniques introduce errors in the output with consumption of more time, hence error free high speed multipliers has to be designed. In this paper we propose FPGA based Recursive Error Free Mitchell Log Multiplier (REFMLM) for image Filters. The 2x2 error free Mitchell log multiplier is designed with zero error by introducing error correction term is used in higher order Karastuba-Ofman Multiplier (KOM) Architectures. The higher order KOM multipliers is decomposed into number of lower order multipliers using radix 2 till basic multiplier block of order 2x2 which is designed by error free Mitchell log multiplier. The 8x8 REFMLM is tested for Gaussian filter to remove noise in fingerprint image. The Multiplier is synthesized using Spartan 3 FPGA family device XC3S1500-5fg320. It is observed that the performance parameters such as area utilization, speed, error and PSNR are better in the case of proposed architecture compared to existing architectures