A Specialized Processor for Track Reconstruction at the LHC Crossing Rate

TL;DR

This paper introduces a specialized FPGA-based processor with a novel pattern-recognition algorithm for real-time, high-precision track reconstruction of hundreds of charged particles at the LHC's full crossing rate, enabling seamless integration with detector readout.

Contribution

The study develops and tests a massively parallel pattern-recognition algorithm inspired by biological visual processing, achieving sub-microsecond latencies for large detector tracking at 40 MHz.

Findings

High-quality tracking with sub-μs latency demonstrated in FPGA implementations.

Algorithm capable of processing hundreds of tracks simultaneously.

Potential for real-time track reconstruction integrated into detector readout.

Abstract

We present the results of an R&D study of a specialized processor capable of precisely reconstructing events with hundreds of charged-particle tracks in pixel detectors at 40 MHz, thus suitable for processing LHC events at the full crossing frequency. For this purpose we design and test a massively parallel pattern-recognition algorithm, inspired by studies of the processing of visual images by the brain as it happens in nature. We find that high-quality tracking in large detectors is possible with sub-$\mu$s latencies when this algorithm is implemented in modern, high-speed, high-bandwidth FPGA devices. This opens a possibility of making track reconstruction happen transparently as part of the detector readout.