Application Specific Cache Simulation Analysis for Application Specific Instruction set Processor

TL;DR

This paper explores the use of application-specific instruction set processor (ASIP) simulators to analyze cache memory configurations tailored to specific applications, enhancing VLSI design efficiency.

Contribution

It demonstrates the implementation of cache simulation using ASIP simulators like SimpleScalar and VEX for customized application-specific memory configurations.

Findings

Cache parameters vary with application requirements

Simulators effectively model cache behavior for ASIP design

Customized cache configurations improve simulation accuracy

Abstract

An Efficient Simulation of application specific instruction-set processors (ASIP) is a challenging onus in the area of VLSI design. This paper reconnoiters the possibility of use of ASIP simulators for ASIP Simulation. This proposed study allow as the simulation of the cache memory design with various ASIP simulators like Simple scalar and VEX. In this paper we have implemented the memory configuration according to desire application. These simulators performs the cache related results such as cache name, sets, cache associativity, cache block size, cache replacement policy according to specific application.