Study on FPGA SEU Mitigation for Readout Electronics of DAMPE BGO Calorimeter

TL;DR

This paper investigates SEU mitigation techniques for FPGA-based readout electronics in DAMPE's BGO calorimeter, implementing a multi-level redundancy design tested with heavy-ion beams to ensure radiation hardness in space.

Contribution

It introduces a novel FPGA design with SEU tolerance using partial TMR, CRC, and reset methods, optimized for low resource consumption in space applications.

Findings

SEU mitigation methods effectively tested with heavy-ion beams

The proposed FPGA design achieves SEU tolerance with low resource use

Enhanced radiation hardness for space-based readout electronics

Abstract

The BGO calorimeter, which provides a wide measurement range of the primary cosmic ray spectrum, is a key sub-detector of Dark Matter Particle Explorer (DAMPE). The readout electronics of calorimeter consists of 16 pieces of Actel ProASIC Plus FLASH-based FPGA, of which the design-level flip-flops and embedded block RAMs are single event upset (SEU) sensitive in the harsh space environment. Therefore to comply with radiation hardness assurance (RHA), SEU mitigation methods, including partial triple modular redundancy (TMR), CRC checksum, and multi-domain reset are analyzed and tested by the heavy-ion beam test. Composed of multi-level redundancy, a FPGA design with the characteristics of SEU tolerance and low resource consumption is implemented for the readout electronics.