Ion traps fabricated in a CMOS foundry

TL;DR

This paper demonstrates the fabrication of surface-electrode ion traps using a standard 90-nm CMOS foundry process, enabling scalable quantum computing hardware with integrated electronics and photonics.

Contribution

First demonstration of ion traps fabricated in a commercial CMOS process, combining trap electrodes with CMOS circuitry for scalable quantum computing.

Findings

Stable ion trapping with a CMOS-fabricated trap.

Motional heating rates comparable to traditional traps.

Potential for integrated quantum processing hardware.

Abstract

We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This is the first demonstration of scalable quantum computing hardware, in any modality, utilizing a commercial CMOS process, and it opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.