Maximum density of quantum information in a scalable CMOS implementation of the hybrid qubit architecture

TL;DR

This paper proposes a scalable CMOS-compatible hybrid qubit architecture using silicon quantum dots, analyzing the maximum density of quantum information achievable with fault-tolerant multi-qubit circuits.

Contribution

It introduces a CMOS-compatible implementation of hybrid qubits and evaluates the maximum logical qubit density for fault-tolerant quantum computing.

Findings

Maximum logical qubit density of 2.6 million qubits per cm².

Implementation of multi-qubit circuits with fault-tolerance capabilities.

Evaluation of resource requirements for scalable quantum error correction.

Abstract

Scalability from single qubit operations to multi-qubit circuits for quantum information processing requires architecture-specific implementations. Semiconductor hybrid qubit architecture is a suitable candidate to realize large scale quantum information processing, as it combines a universal set of logic gates with fast and all-electrical manipulation of qubits. We propose an implementation of hybrid qubits, based on Si Metal-Oxide-Semiconductor (MOS) quantum dots, compatible with the CMOS industrial technologic standards. We discuss the realization of multi-qubit circuits capable of fault-tolerant computation and quantum error correction, by evaluating the time and space resources needed for their implementation. As a result, the maximum density of quantum information is extracted from a circuit including 8 logical qubits encoded by the [[7,1,3]] Steane code. The corresponding surface density of logical qubits is 2.6 Mqubit/cm$^2$.