Impact of gate leakage considerations in tunnel field effect transistor design

TL;DR

This study investigates how gate leakage through thin dielectrics affects the subthreshold performance of tunnel FETs at low voltages, emphasizing the importance of including leakage considerations in device design.

Contribution

It provides a detailed simulation-based analysis of gate leakage effects on TFET subthreshold characteristics and highlights the necessity of accounting for leakage in design strategies.

Findings

Gate leakage significantly degrades TFET subthreshold parameters.

Drain-offset and short-gate methods reduce leakage but are insufficient without leakage consideration.

Ignoring gate tunneling leakage leads to underestimating off-state current in TFETs.

Abstract

In this paper, we have presented the impact of the gate leakage through thin gate dielectrics (SiO2 and high-\k{appa} gate dielectric) on the subthreshold characteristics of the tunnel field effect transistors (TFET) for a low operating voltage of 0.5 V. Using calibrated two-dimensional simulations it is shown that even for such a low operating voltage, the gate leakage substantially degrades several subthreshold parameters of the TFET such as the off-state current, minimum subthreshold swing and average subthreshold swing. While the drain-offset as well as the short-gate are effective methods for reducing the gate leakage, we show that if the gate tunneling leakage is not considered, even for these two methods, the overall TFET off-state current will be significantly underestimated. Our results demonstrate the need to carefully account for the gate leakage in the design of TFETs just as it is done for the conventional nanoscale MOSFETs.