A Tiling Perspective for Register Optimization

TL;DR

This paper introduces a novel instruction tiling approach for register allocation that unifies loop unrolling, promotion, and instruction scheduling, leading to improved register pressure management.

Contribution

It presents a new unified framework using instruction tiling and constraint programming to optimize register allocation considering loop unrolling and instruction scheduling.

Findings

Demonstrates improvements over state-of-the-art methods on SPEC benchmarks.

Effectively manages register pressure within innermost loops.

Provides a scalable approach for loop optimization.

Abstract

Register allocation is a much studied problem. A particularly important context for optimizing register allocation is within loops, since a significant fraction of the execution time of programs is often inside loop code. A variety of algorithms have been proposed in the past for register allocation, but the complexity of the problem has resulted in a decoupling of several important aspects, including loop unrolling, register promotion, and instruction reordering. In this paper, we develop an approach to register allocation and promotion in a unified optimization framework that simultaneously considers the impact of loop unrolling and instruction scheduling. This is done via a novel instruction tiling approach where instructions within a loop are represented along one dimension and innermost loop iterations along the other dimension. By exploiting the regularity along the loop dimension, and imposing essential dependence based constraints on intra-tile execution order, the problem of optimizing register pressure is cast in a constraint programming formalism. Experimental results are provided from thousands of innermost loops extracted from the SPEC benchmarks, demonstrating improvements over the current state-of-the-art.