A Tiling Perspective for Register Optimization
Lukasz Domagala (INRIA Grenoble Rh\^one-Alpes), Fabrice Rastello, (INRIA Grenoble Rh\^one-Alpes), Sadayappan Ponnuswany, Duco Van Amstel (INRIA, Grenoble Rh\^one-Alpes)

TL;DR
This paper introduces a novel instruction tiling approach for register allocation that unifies loop unrolling, promotion, and instruction scheduling, leading to improved register pressure management.
Contribution
It presents a new unified framework using instruction tiling and constraint programming to optimize register allocation considering loop unrolling and instruction scheduling.
Findings
Demonstrates improvements over state-of-the-art methods on SPEC benchmarks.
Effectively manages register pressure within innermost loops.
Provides a scalable approach for loop optimization.
Abstract
Register allocation is a much studied problem. A particularly important context for optimizing register allocation is within loops, since a significant fraction of the execution time of programs is often inside loop code. A variety of algorithms have been proposed in the past for register allocation, but the complexity of the problem has resulted in a decoupling of several important aspects, including loop unrolling, register promotion, and instruction reordering. In this paper, we develop an approach to register allocation and promotion in a unified optimization framework that simultaneously considers the impact of loop unrolling and instruction scheduling. This is done via a novel instruction tiling approach where instructions within a loop are represented along one dimension and innermost loop iterations along the other dimension. By exploiting the regularity along the loop…
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Taxonomy
TopicsParallel Computing and Optimization Techniques · Distributed and Parallel Computing Systems · Constraint Satisfaction and Optimization
