Parallelism Via Concurrency at Multiple Levels

TL;DR

This paper explores how combining hardware and software concurrency at multiple levels can optimize computing performance by reducing latency and increasing parallelism.

Contribution

It analyzes the interplay between hardware and software concurrency to enhance performance, emphasizing the importance of both for optimal parallel execution.

Findings

Software concurrency must complement hardware parallelism for best performance

Increasing chip frequency alone is insufficient for optimal performance

Effective parallelism reduces latency and improves output quality

Abstract

In this paper we examine the key elements determining the best performance of computing by increasing the frequency of a single chip and to get the minimum latency during execution of the programs to achieve best possible output. It is not enough to provide concurrent improvements in the hardware as Software also have to introduce concurrency in order to exploit the parallelism. The software parallelism is defined by the control and data dependency of programs whereas Hardware refers to the type of parallelism defined by the machine architecture and hardware multiplicity.