Self-consistent $\textbf{k}\cdot \textbf{p}$ calculations for gated thin layers of 3D Topological Insulators

TL;DR

This paper presents a theoretical analysis of how gate voltage influences the electronic properties of thin layers of 3D topological insulators, highlighting the effects on surface states and bulk carriers.

Contribution

It introduces a self-consistent k·p calculation method to study gate effects on quasi-3D HgTe layers, revealing new insights into surface and bulk state behaviors.

Findings

Surface states dominate transport properties.

Bulk charge carriers emerge under gate voltage.

Bottom surface properties are unaffected by gating due to screening.

Abstract

Topological protected surface states are one of the hallmarks of three-dimensional topological insulators. In this work we theoretically analyze the gate-voltage-effects on a quasi-3D layer of HgTe. We find that while the gapless surface states dominate the transport, as an external gate voltage is applied, the existence of bulk charge carriers is likely to occur. We also find that due to screening effects, physical properties that arise from the bottom surface are gate-voltage independent. Finally, we point out the experimental signatures that characterize these effects.