Evaluating the Self-Optimization Process of the Adaptive Memory Management Architecture Self-aware Memory
Oliver Mattes, Wolfgang Karl

TL;DR
This paper presents a decentralized, self-optimizing memory architecture called Self-aware Memory (SaM) designed for manycore systems, demonstrating that its adaptive optimization process improves runtime efficiency despite overhead.
Contribution
It introduces the concept of ongoing decentralized self-optimization in memory management and evaluates its parameters for the first time.
Findings
Overhead of self-optimization is offset by runtime improvements.
Proper parameter tuning enhances the efficiency of the adaptive process.
Decentralized approach offers scalability and flexibility in memory management.
Abstract
With the continuously increasing integration level, manycore processor systems are likely to be the coming system structure not only in HPC but also for desktop or mobile systems. Nowadays manycore processors like Tilera TILE, KALRAY MPPA or Intel SCC combine a rising number of cores in a tiled architecture and are mainly designed for high performance applications with focus on direct inter-core communication. The current architectures have limitations by central or sparse components like memory controllers, memory I/O or inflexible memory management. In the future highly dynamic workloads with multiple concurrently running applications, changing I/O characteristics and a not predictable memory usage have to be utilized on these manycore systems. Consequently the memory management has to become more flexible and distributed in nature and adaptive mechanisms and system structures are…
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Taxonomy
TopicsParallel Computing and Optimization Techniques · Embedded Systems Design Techniques · Real-Time Systems Scheduling
