G4LTL-ST: Automatic Generation of PLC Programs

TL;DR

G4LTL-ST automatically generates IEC 61131-3 Structured Text control code for industrial PLCs from complex timed behavioral specifications expressed in extended linear temporal logic, simplifying control design.

Contribution

It introduces a novel synthesis algorithm that handles non-linear and timing constraints, and supports engineers in refining specifications for realizability.

Findings

Successfully synthesizes control code from complex LTL specifications.

Supports non-linear arithmetic and timing constraints in synthesis.

Provides guidance for engineers to refine specifications when synthesis fails.

Abstract

G4LTL-ST automatically synthesizes control code for industrial Programmable Logic Controls (PLC) from timed behavioral specifications of input-output signals. These specifications are expressed in a linear temporal logic (LTL) extended with non-linear arithmetic constraints and timing constraints on signals. G4LTL-ST generates code in IEC 61131-3-compatible Structured Text, which is compiled into executable code for a large number of industrial field-level devices. The synthesis algorithm of G4LTL-ST implements pseudo-Boolean abstraction of data constraints and the compilation of timing constraints into LTL, together with a counterstrategy-guided abstraction refinement synthesis loop. Since temporal logic specifications are notoriously difficult to use in practice, G4LTL-ST supports engineers in specifying realizable control problems by suggesting suitable restrictions on the behavior of the control environment from failed synthesis attempts.