Design of a capacitor-less low-dropout voltage regulator
X. R. Li, D.B. Pei, Q. Liu, R.Shen
TL;DR
This paper presents a novel capacitor-less low-dropout voltage regulator design that ensures stability with minimal external components, fast transient response, and low quiescent current, suitable for power-sensitive applications.
Contribution
The paper introduces a stable capacitor-less LDO design using Miller compensation and an extra transient circuit, improving response time and reducing voltage spikes.
Findings
Phase margin exceeds 50 degrees at full load
Peak voltage during load change is 40mV
Quiescent current is only 45μA
Abstract
A solution to the stability of capacitor-less low-dropout regulators with a 4pF Miller capacitor in Multi-level current amplifier is proposed. With the Miller compensation, a more than 50{\deg}phase margin is guaranteed in full load. An extra fast transient circuit is adopted to reduce stable time and peak voltage. When the load changes from light to heavy, the peak voltage is 40mV and chip quiescent current is only 45uA.
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
Taxonomy
TopicsAnalog and Mixed-Signal Circuit Design · Low-power high-performance VLSI design · Advancements in Semiconductor Devices and Circuit Design