Multiplierless Approximate 4-point DCT VLSI Architectures for Transform Block Coding

TL;DR

This paper presents two multiplierless 4x4 approximate DCT algorithms and their FPGA implementations, achieving real-time processing at 1 GHz with low power consumption for digital video transform coding.

Contribution

It introduces novel multiplierless algorithms for 4x4 DCT and demonstrates their efficient FPGA-based hardware implementations for real-time video processing.

Findings

Real-time operation at 1 GHz achieved

Low power consumption under 120 mW demonstrated

Effective FPGA implementation for 4x4 DCT

Abstract

Two multiplierless algorithms are proposed for 4x4 approximate-DCT for transform coding in digital video. Computational architectures for 1-D/2-D realisations are implemented using Xilinx FPGA devices. CMOS synthesis at the 45 nm node indicate real-time operation at 1 GHz yielding 4x4 block rates of 125 MHz at less than 120 mW of dynamic power consumption.