Design and considerations of ADC0808 as interleaved ADCs

TL;DR

This paper presents a calibration technique for time interleaved ADC systems using ADC0808 chips, addressing timing and gain mismatches to improve high-speed data conversion accuracy.

Contribution

It introduces a novel calibration method for linear and nonlinear channel mismatches, including foreground and background identification techniques for dynamic mismatch correction.

Findings

Effective calibration of timing and gain mismatches achieved

Improved accuracy in high-speed ADC systems demonstrated

Unified model for linear and nonlinear channel mismatches

Abstract

Here in this paper we are presenting a digital system background technique for correcting the time offset error rate and gain mismatches in a time interleaved analog to digital converter system for N channel communication using 8 bit ADC0808 ICs. A time interleaved A to D converter system is an effective way to implement a high sampling rate ADC with relatively slow circuits. This paper analyses the benefits and derives an upper band on the performance by considering kT/C noise and slewing requirement of the circuit driving the system. In the system, several channel ADCs operate at interleaved sampling times as if they were effectively a single ADC operating at a much higher sampling rate. A timing mismatch calibration technique is proposed that covers linear and non linear channel mismatches, unifies, and extends the channel models. A novel foreground channel mismatch identification method has been developed, which can be used to fully characterize dynamic linear mismatches. A background identification method provides accurate timing mismatch estimates.