Design of a Low Voltage Class-AB CMOS Super Buffer Amplifier with Sub Threshold and Leakage Control

TL;DR

This paper presents a low-voltage CMOS super buffer with reduced leakage and area, employing a novel transistor gating technique to achieve high drive capability and low static power consumption at 45nm technology.

Contribution

Introduces a transistor gating technique for low leakage in CMOS class-AB buffers, improving power efficiency and area without sacrificing speed.

Findings

Leakage power reduced by 1.105%

Area decreased by 3.08%

Simulated at 45nm CMOS technology at 3.3V

Abstract

This paper describes a CMOS analogy voltage supper buffer designed to have extremely low static current Consumption as well as high current drive capability. A new technique is used to reduce the leakage power of class-AB CMOS buffer circuits without affecting dynamic power dissipation. The name of applied technique is TRANSISTOR GATING TECHNIQUE, which gives the high speed buffer with the reduced low power dissipation (1.105%), low leakage and reduced area (3.08%) also. The proposed buffer is simulated at 45nm CMOS technology and the circuit is operated at 3.3V supply[11]. Consumption is comparable to the switching component. Reports indicate that 40% or even higher percentage of the total power consumption is due to the leakage of transistors. This percentage will increase with technology scaling unless effective techniques are introduced to bring leakage under control. This article focuses on circuit optimization and Design automation techniques to accomplish this goal [9].