FPGA design of a cdma2000 turbo decoder
Maribell Sacanamboy Franco, Fabio G. Guerrero

TL;DR
This paper details the FPGA implementation of a cdma2000 turbo decoder using the MAX-Log-MAP algorithm, analyzing hardware design trade-offs and presenting decoding results for 250-bit packets.
Contribution
It introduces an FPGA hardware design for cdma2000 turbo decoding based on MAX-Log-MAP, including analysis of area, performance, and key design variables.
Findings
Decoding of 250-bit packets achieved.
Trade-off analysis between area and performance.
Key hardware design variables identified.
Abstract
This paper presents the FPGA hardware design of a turbo decoder for the cdma2000 standard. The work includes a study and mathematical analysis of the turbo decoding process, based on the MAX-Log-MAP algorithm. Results of decoding for a packet size of two hundred fifty bits are presented, as well as an analysis of area versus performance, and the key variables for hardware design in turbo decoding.
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Taxonomy
TopicsAdvanced Wireless Communication Techniques · Error Correcting Code Techniques · Cellular Automata and Applications
