Metal-Gated Junctionless Nanowire Transistors

TL;DR

This paper investigates metal-gated high-k dielectric junctionless nanowire transistors using detailed simulations, aiming to overcome limitations of polysilicon gates and enable scalable, simplified nano-architectures.

Contribution

It introduces novel metal-gated high-k JNFETs and demonstrates their potential advantages through comprehensive process and device simulations.

Findings

Metal-gated high-k JNFETs show improved electrical characteristics.

Simulation results indicate better scalability and compatibility with nano-architectures.

Potential for simplified fabrication without additional ion implantation.

Abstract

Junctionless Nanowire Field-Effect Transistors (JNFETs), where the channel region is uniformly doped without the need for source-channel and drain-channel junctions or lateral doping abruptness, are considered an attractive alternative to conventional CMOS FETs. Previous theoretical and experimental works [1][2] on JNFETs have considered polysilicon gates and silicon-dioxide dielectric. However, with further scaling, JNFETs will suffer from deleterious effects of doped polysilicon such as high resistance, additional capacitance due to gate-oxide interface depletion, and incompatibility with high-k dielectrics[3][4]. In this paper, novel metal- gated high-k JNFETs are investigated through detailed process and device simulations. These MJNFETs are also ideally suited for new types of nano-architectures such as N3ASICs [5] which utilize regular nanowire arrays with limited customization. In such nano- systems, the simplified device geometry in conjunction with a single-type FET circuit style [6] would imply that logic arrays could be patterned out of pre-doped SOI wafers without the need for any additional ion implantation.