A Flexible Design for Optimization of Hardware Architecture in Distributed Arithmetic based FIR Filters

TL;DR

This paper proposes a flexible hardware architecture for distributed arithmetic based FIR filters, optimizing LUTs and compressors to significantly reduce delay in high-order filter implementations.

Contribution

It introduces a novel, optimized hardware design for DA-based FIR filters using dynamic programming, improving delay performance over previous structures.

Findings

Delay reduction of 16%-62.5% compared to prior designs

Efficient combination of LUTs and compressors

System-level optimization via dynamic programming

Abstract

FIR filters are used in many performance/power critical applications such as mobile communication devices, analogue to digital converters and digital signal processing applications. Design of appropriate FIR filters usually causes the order of filter to be increased. Synthesis and tape-out of high-order FIR filters with reasonable delay, area and power has become an important challenge for hardware designers. In many cases the complexity of high-order filters causes the constraints of the total design could not be satisfied. In this paper, efficient hardware architecture is proposed for distributed arithmetic (DA) based FIR filters. The architecture is based on optimized combination of Look-up Tables (LUTs) and compressors. The optimized system level solution is obtained from a set of dynamic programming optimization algorithms. The experiments show the proposed design educed the delay cost between 16%-62.5% in comparison of previous optimized structures for DA-based architectures.