A High-Performance Triple Patterning Layout Decomposer with Balanced Density

TL;DR

This paper introduces a high-performance triple patterning lithography layout decomposer that incorporates density balancing throughout its process, improving density distribution and reducing edge placement errors without increasing conflicts or stitches.

Contribution

The paper presents a novel TPL layout decomposer that seamlessly integrates density balancing into all key steps, enhancing performance and density uniformity compared to prior methods.

Findings

Achieves higher performance than previous state-of-the-art decomposers.

Provides more balanced density leading to fewer edge placement errors.

Maintains similar conflict and stitch counts as non-balanced methods.

Abstract

Triple patterning lithography (TPL) has received more and more attentions from industry as one of the leading candidate for 14nm/11nm nodes. In this paper, we propose a high performance layout decomposer for TPL. Density balancing is seamlessly integrated into all key steps in our TPL layout decomposition, including density-balanced semi-definite programming (SDP), density-based mapping, and density-balanced graph simplification. Our new TPL decomposer can obtain high performance even compared to previous state-of-the-art layout decomposers which are not balanced-density aware, e.g., by Yu et al. (ICCAD'11), Fang et al. (DAC'12), and Kuang et al. (DAC'13). Furthermore, the balanced-density version of our decomposer can provide more balanced density which leads to less edge placement error (EPE), while the conflict and stitch numbers are still very comparable to our non-balanced-density baseline.