Methodology for standard cell compliance and detailed placement for triple patterning lithography

TL;DR

This paper introduces a comprehensive framework for standard cell compliance and detailed placement that incorporates triple patterning lithography constraints early in the design process, improving layout decomposability and conflict resolution.

Contribution

It presents a novel TPL-aware design methodology that integrates standard cell compliance and placement to enhance manufacturability at sub-16nm nodes.

Findings

Reduces TPL conflicts significantly compared to traditional flows.

Maintains critical path delay with negligible impact.

Enables simultaneous layout decomposition and placement.

Abstract

As the feature size of semiconductor process further scales to sub-16nm technology node, triple patterning lithography (TPL) has been regarded one of the most promising lithography candidates. M1 and contact layers, which are usually deployed within standard cells, are most critical and complex parts for modern digital designs. Traditional design flow that ignores TPL in early stages may limit the potential to resolve all the TPL conflicts. In this paper, we propose a coherent framework, including standard cell compliance and detailed placement to enable TPL friendly design. Considering TPL constraints during early design stages, such as standard cell compliance, improves the layout decomposability. With the pre-coloring solutions of standard cells, we present a TPL aware detailed placement, where the layout decomposition and placement can be resolved simultaneously. Our experimental results show that, with negligible impact on critical path delay, our framework can resolve the conflicts much more easily, compared with the traditional physical design flow and followed layout decomposition.