Performance Evaluation of ECC in Single and Multi Processor Architectures on FPGA Based Embedded System

TL;DR

This paper evaluates the performance of Elliptic Curve Cryptography (ECC) implemented on FPGA-based embedded systems, comparing single and multi-processor architectures to optimize throughput, resource use, and power consumption.

Contribution

It is the first study to explore ECC implementation on FPGA with both single and dual processor cores involving task parallelization for embedded systems.

Findings

ECC implementation varies significantly between single and dual processor architectures.

Task parallelization improves throughput and resource utilization.

The study provides insights into optimal FPGA architectural configurations for ECC.

Abstract

Cryptographic algorithms are computationally costly and the challenge is more if we need to execute them in resource constrained embedded systems. Field Programmable Gate Arrays (FPGAs) having programmable logic de- vices and processing cores, have proven to be highly feasible implementation platforms for embedded systems providing lesser design time and reconfig- urability. Design parameters like throughput, resource utilization and power requirements are the key issues. The popular Elliptic Curve Cryptography (ECC), which is superior over other public-key crypto-systems like RSA in many ways, such as providing greater security for a smaller key size, is cho- sen in this work and the possibilities of its implementation in FPGA based embedded systems for both single and dual processor core architectures in- volving task parallelization have been explored. This exploration, which is first of its kind considering the other existing works, is a needed activity for evaluating the best possible architectural environment for ECC implementa- tion on FPGA (Virtex4 XC4VFX12, FF668, -10) based embedded platform.