Cache-aware static scheduling for hard real-time multicore systems based on communication affinities

TL;DR

This paper introduces a cache-aware static scheduling method for hard real-time multicore systems that minimizes L1 cache misses by leveraging communication affinities, improving worst-case performance.

Contribution

It presents a novel mathematical formulation for static scheduling that optimally reduces cache misses based on communication affinities in multicore architectures.

Findings

Effective reduction in L1 cache misses demonstrated

Scheduling improves worst-case task performance

Method applicable to complex multicore cache hierarchies

Abstract

The growing need for continuous processing capabilities has led to the development of multicore systems with a complex cache hierarchy. Such multicore systems are generally designed for improving the performance in average case, while hard real-time systems must consider worst-case scenarios. An open challenge is therefore to efficiently schedule hard real-time tasks on a multicore architecture. In this work, we propose a mathematical formulation for computing a static scheduling that minimize L1 data cache misses between hard real-time tasks on a multicore architecture using communication affinities.