Evaluating Cache Coherent Shared Virtual Memory for Heterogeneous Multicore Chips

TL;DR

This paper proposes a cache-coherent shared virtual memory design for heterogeneous multicore chips combining CPUs and GPUs, along with an extension of pthreads, to evaluate potential performance improvements in such architectures.

Contribution

It introduces a CCSVM design tailored for CPU/MTTOP chips and extends the pthreads model to support programming this heterogeneous system.

Findings

Potential performance benefits of CCSVM in HMCs evaluated.

Design facilitates programming of heterogeneous cores with shared memory.

Extension of pthreads enables effective utilization of the proposed architecture.

Abstract

The trend in industry is towards heterogeneous multicore processors (HMCs), including chips with CPUs and massively-threaded throughput-oriented processors (MTTOPs) such as GPUs. Although current homogeneous chips tightly couple the cores with cache-coherent shared virtual memory (CCSVM), this is not the communication paradigm used by any current HMC. In this paper, we present a CCSVM design for a CPU/MTTOP chip, as well as an extension of the pthreads programming model, called xthreads, for programming this HMC. Our goal is to evaluate the potential performance benefits of tightly coupling heterogeneous cores with CCSVM.