Partial Sums Computation In Polar Codes Decoding

TL;DR

This paper presents an efficient hardware architecture for partial sums computation in polar codes decoding, improving speed and resource usage by modeling the process as matrix multiplication.

Contribution

It introduces a novel hardware implementation of partial sums computation as matrix multiplication, reducing logic resources and eliminating multiplexing overhead.

Findings

Reduced logic resource consumption in hardware implementation

Elimination of multiplexing resources in partial sums computation

Formal architectures for partial sums and generator matrix bits generation

Abstract

Polar codes are the first error-correcting codes to provably achieve the channel capacity but with infinite codelengths. For finite codelengths the existing decoder architectures are limited in working frequency by the partial sums computation unit. We explain in this paper how the partial sums computation can be seen as a matrix multiplication. Then, an efficient hardware implementation of this product is investigated. It has reduced logic resources and interconnections. Formalized architectures, to compute partial sums and to generate the bits of the generator matrix k^n, are presented. The proposed architecture allows removing the multiplexing resources used to assigned to each processing elements the required partial sums.