Using Chip Multithreading to Speed Up Scenario-Based Design Space Exploration

TL;DR

This paper explores how chip multithreading can accelerate scenario-based design space exploration for embedded systems by porting and analyzing its performance on a SPARC T3-4 server.

Contribution

It demonstrates the adaptation and performance analysis of a design space exploration method on a multithreaded server platform.

Findings

Significant speedup in exploration time on SPARC T3-4

Insights into performance behavior of DSE on multithreaded architecture

Validation of porting approach for embedded system design tools

Abstract

To cope with the complex embedded system design, early design space exploration (DSE) is used to make design decisions early in the design phase. For early DSE it is crucial that the running time of the exploration is as small as possible. In this paper, we describe both the porting of our scenario-based DSE to the SPARC T3-4 server and the analysis of its performance behavior.